1. Field of the Invention
The disclosed technology relates generally to methods of fabricating field-effect semiconductor devices, such as field-effect transistors (FETs), and more particularly to methods of fabricating field effect semiconductor devices using a replacement gate process.
2. Description of the Related Technology
Scaling of semiconductor devices to integrate more devices per unit area continue to pose new challenges. In particular, for scaling of field-effect transistors (FET), as gate lengths continue to scale down, the structural design of offset spacers, sometimes referred to as sidewall spacers, is becoming increasingly critical for transistor performance. The desired dimensions of such dielectric offset spacers designed to meet certain performance targets are becoming increasingly smaller and the corresponding process designs are becoming increasingly difficult in order to achieve the desired critical dimensions.
Therefore, there is a need to address the increased sensitivity to gate spacer dimensioning using process techniques for gate sidewall spacer formation, particularly in manufacturing processes following a gate-last approach, sometimes referred to as a “replacement gate” process or a “damascene gate” process.
US patent application, for example, 2007/0287259 A1 discloses the use of gate isolation spacers in a method of forming a semiconductor structure according to a replacement gate process.
Also, in US patent application 2006/0148182 A1, a self-aligned source/drain quantum well transistor or high charge carrier mobility transistor is formed using a replacement metal gate process, in which sidewall spacers temporarily bracket a dummy gate electrode.
Implant-free devices where source/drain (S/D) junctions are placed by an offset spacer, and which comprise doped source/drain regions epitaxially grown with limited diffusion, e.g. extremely thin silicon on insulator (ET-SOI) devices and implant free quantum well devices (e.g. U.S. Pat. No. 7,915,608 B2), show a very strong sensitivity towards the offset spacer critical dimension (CD). The offset spacer CD needs to be minimized to limit increase in external resistance and subsequent reduction in drive current, while it cannot be made too small to avoid high leakage between gate and drain. Careful process control is therefore desired. On 3D devices as for instance FINFET devices, this CD control along the FIN sidewall is even more challenging.
A problem with the current techniques for fabricating FET devices is still that they lack a precise control of the distance from the source/drain extensions to the gate edge.